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SAA7102; SAA7103
Digital video encoder
Rev. 04 -- 18 January 2006 Product data sheet
1. General description
The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800 x 600 resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 800 x 600 resolution/60 Hz (PIXCLK < 45 MHz). The device includes a sync/clock generator and on-chip DACs.
2. Features
Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC 27 MHz crystal-stable subcarrier generation Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip or from external source Up to 800 x 600 graphics data at 60 Hz or 50 Hz with programmable underscan range. Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) (signals in parenthesis are optional); all at 10-bit resolution Non-Interlaced (NI) CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling Downscaling from 1 : 1 to 1 : 2 and up to 20 % upscaling Optional interlaced CB-Y-CR input of Digital Versatile Disc (DVD) signals Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with maximum 45 MHz) 3 x 256 bytes RGB Look-Up Table (LUT) Support for hardware cursor Programmable border color of underscan area On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) Fast I2C-bus control port (400 kHz) Encoder can be master or slave Programmable horizontal and vertical input synchronization phase Programmable horizontal sync output phase Internal Color Bar Generator (CBG) Optional support of various Vertical Blanking Interval (VBI) data insertion
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to the SAA7102 only Power-save modes Joint Test Action Group (JTAG) Boundary Scan Test (BST) Monolithic CMOS 3.3 V device, 5 V tolerant I/Os QFP44 and LBGA156 packages Same footprint as SAA7108E; SAA7109E
3. Quick reference data
Table 1: Symbol VDDA VDDD IDDA IDDD Vi Vo(p-p) Quick reference data Parameter analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog CVBS output signal voltage for a 100/100 color bar at 75/2 load (peak-to-peak value) load resistance low frequency integral linearity error of DACs low frequency differential linearity error of DACs ambient temperature Conditions Min 3.15 3.0 1 1 Typ 3.3 3.3 110 70 1.23 Max 3.45 3.6 140 90 Unit V V mA mA V
TTL compatible
RL ILElf(DAC) DLElf(DAC) Tamb
0
37.5 -
3 1 70
LSB LSB C
4. Ordering information
Table 2: Ordering information Package Name SAA7102E SAA7103E SAA7102H SAA7103H QFP44 LBGA156 Description plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm Version SOT700-1 SOT307-2 Type number
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
2 of 84
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Product data sheet Rev. 04 -- 18 January 2006
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. SAA7102_SAA7103_4
5. Block diagram
Philips Semiconductors
VDDD2 VDDD1 10 4 to 1, 44 to 41, 16 to 19 VSSD1 9 40 VSSD2 39
VDDA2 VDDA1 36 29
VSSA1 DUMP 33 32
RSET TDI 31 38
TRST TCK 37 8
TDO TMS 7 6
PD11 to PD0
INPUT FORMATTER
RGB LUT (OR BYPASS)
CURSOR INSERTION
RGB TO Y-CB-CR MATRIX (OR BYPASS)
PIXCLKI
15
DECIMATOR 4 : 4 : 4 to 4 : 2 : 2 (OR BYPASS)
HORIZONTAL SCALER
VERTICAL SCALER AND ANTI-FLICKER FILTER
FIFO
30 BORDER GENERATOR VIDEO ENCODER TRIPLE DAC 28 27 26 PIXCLKO 20 CGC LOW-PASS OSCILLATOR/ DTO TIMING GENERATOR I2C-BUS CONTROL 25
BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C HSM_CSYNC
SAA7102H SAA7103H
SAA7102; SAA7103
VSM
23
35 XTALI
34 XTALO
13
14
21
22
24
12 SDA
11
5 RESET
mhb963
VSVGC TTX_SRES 27 MHz FSVGC
HSVGC
CBO TTXRQ_XCLKO2
SCL
Digital video encoder
3 of 84
Fig 1. Block diagram (SAA7102H and SAA7103H)
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
6. Pinning information
6.1 Pinning
ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P
SAA7102E SAA7103E
001aad559
Transparent top view
Fig 2. Pin configuration (LBGA156)
PD8 PD9 PD10 PD11 RESET TMS TDO TCK VSSD1
1 2 3 4 5 6 7 8 9
34 XTALO 33 VSSA1 32 DUMP 31 RSET 30 BLUE_CB_CVBS 29 VDDA1 28 GREEN_VBS_CVBS 27 RED_CR_C 26 HSM_CSYNC 25 VSM 24 TTXRQ_XCLKO2 23 TTX_SRES HSVGC 22
001aad558
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
40 VDDD2
36 VDDA2 PIXCLKO 20
39 VSSD2
SAA7102H SAA7103H
VDDD1 10 SCL 11 SDA 12 FSVGC 13 VSVGC 14 PIXCLKI 15 PD3 16 PD2 17 PD1 18 PD0 19 CBO 21
Fig 3. Pin configuration (QFP44)
SAA7102_SAA7103_4
Product data sheet
Rev. 04 -- 18 January 2006
35 XTALI
37 TRST
44 PD7
43 PD6
42 PD5
41 PD4
38 TDI
4 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Pin allocation table SAA7102E; SAA7103E Symbol PD7 TRST XTALO VSSA1 VDDA1 PD8 PD6 VDDA2 VSSA1 PD11 TTX_SRES VSSD2 GREEN_VBS_CVBS VDDA1 RESET VDDD2 VDDA2 HSM_CSYNC TCK HSVGC VSVGC PD3 FSVGC CBO PD2 PD0 Pin A3 A5 A7 A9 B1 B3 B5 B7 B9 C2 C4 C6 C8 D1 D3 D5 D7 D9 E2 E4 F2 F4 G2 G4 H2 Symbol PD4 XTALI DUMP RSET PD9 PD5 TDI DUMP VDDA1 PD10 TTXRQ_XCLKO2 BLUE_CB_CVBS RED_CR_C TDO TMS VSSD2 VSM VDDA1 SCL VSSD1 PIXCLKI VDDD1 SDA PIXCLKO PD1
Table 3: Pin A2 A4 A6 A8 A10 B2 B4 B6 B8 C1 C3 C5 C7 C9 D2 D4 D6 D8 E1 E3 F1 F3 G1 G3 H1 H3
6.2 Pin description
Table 4: Symbol PD8 PD9 PD10 PD11 RESET TMS TDO TCK VSSD1
SAA7102_SAA7103_4
Pin description Pin LBGA156 QFP44 B2 B1 C2 C1 D2 D3 D1 E1 E4 1 2 3 4 5 6 7 8 9 I I I I I I O I S see Table 28 to Table 33 for pin assignment see Table 28 to Table 33 for pin assignment see Table 28 to Table 33 for pin assignment see Table 28 to Table 33 for pin assignment reset input; active LOW test mode select input for BST [2] test data output for BST [2] test clock input for BST [2] digital ground 1 (peripheral cells)
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Type [1] Description
Product data sheet
Rev. 04 -- 18 January 2006
5 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Pin description ...continued Pin LBGA156 QFP44 F4 E2 G2 G1 F1 F2 F3 H1 H2 H3 G4 G3 E3 C3 C4 D7 D8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Type [1] Description S I(/O) I/O I/O I/O I I I I I O O I/O I O O O digital supply voltage 1 (3.3 V for peripheral cells) serial clock input (I2C-bus) with inactive output path serial data input/output (I2C-bus) frame synchronization output to Video Graphics Controller (VGC) (optional input) [3] vertical synchronization output to VGC (optional input) [3] pixel clock input (looped through) MSB - 4 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB - 5 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB - 6 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB - 7 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment pixel clock output to VGC composite blanking output to VGC; active LOW [3] horizontal synchronization output to VGC (optional input) [3] teletext input or sync reset input teletext request output or 13.5 MHz clock output of the crystal oscillator [3] vertical synchronization output to monitor (non-interlaced auxiliary RGB) horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or composite sync for RGB-SCART analog output of RED or CR or C signal analog output of GREEN or VBS or CVBS signal analog supply voltage 1 (3.3 V for DACs) analog output of BLUE or CB or CVBS signal DAC reference pin; connected via 1 k resistor to analog ground (do not use capacitor in parallel with 1 k resistor) DAC reference pin; connected via 12 resistor to analog ground analog ground 1 crystal oscillator output crystal oscillator input
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table 4: Symbol VDDD1 SCL SDA FSVGC VSVGC PIXCLKI PD3 PD2 PD1 PD0 PIXCLKO CBO HSVGC
TTX_SRES TTXRQ_XCLKO2 VSM HSM_CSYNC
RED_CR_C
C8
27 28 29 30 31
O O S O O
GREEN_VBS_CVBS C7 VDDA1 BLUE_CB_CVBS RSET A10, B9, C9, D9 C6 A9
DUMP VSSA1 XTALO XTALI
SAA7102_SAA7103_4
A7, B7 A8, B8 A6 A5
32 33 34 35
O S O I
Product data sheet
Rev. 04 -- 18 January 2006
6 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Pin description ...continued Pin LBGA156 QFP44 B6, D6 A4 B5 C5, D5 D4 A3 B3 B4 A2 36 37 38 39 40 41 42 43 44 Type [1] Description S I I S S I I I I analog supply voltage 2 (3.3 V for DACs and oscillator) test reset input for BST; active LOW [2] [4] [5] test data input for BST [2] digital ground 2 digital supply voltage 2 (3.3 V for core) MSB - 3 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB - 2 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB - 1 with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment MSB with CB-Y-CR 4 : 2 : 2; see Table 28 to Table 33 for pin assignment
Table 4: Symbol VDDA2 TRST TDI VSSD2 VDDD2 PD4 PD5 PD6 PD7
[1] [2] [3] [4] [5]
Pin type: I = input, O = output, S = supply. In accordance with the "IEEE1149.1" standard the pins TDI, TMS, TCK and TRST are input pins with an internal pull-up resistor and TDO is a 3-state output pin. Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1. For board design without boundary scan implementation connect TRST to ground. This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
7. Functional description
The digital video encoder encodes digital luminance and color difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The SAA7102; SAA7103 can be directly connected to a PC video graphics controller with a maximum resolution of 800 x 600 at a 50 Hz or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Table 28 to Table 33. A complete 3 x 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port Pixel Data (PD) or via the I2C-bus. The SAA7102; SAA7103 supports a 32-bit x 32-bit x 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed.
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
7 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Besides the applications for video output, the SAA7102; SAA7103 can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. The basic encoder function consists of subcarrier generation, color modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/color difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "ITU-R BT.470-3". For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figure 6 to Figure 11. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals. The 8-bit multiplexed CB-Y-CR formats are "ITU-R BT.656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in Slave mode. For assignment of the input data to the rising or falling clock edge see Table 28 to Table 34. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7102; SAA7103 synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Figure 15). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as:
* Black and blanking level control * Color subcarrier frequency * Variable burst amplitude etc.
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
8 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
7.1 Reset conditions
To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 5.
Table 5: Pin FSVGC VSVGC CBO HSVGC TTXRQ_XCLKO2 Strapping pins Tied LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH Preset NTSC M encoding, PIXCLK fits to 640 x 480 graphics input PAL B/G encoding, PIXCLK fits to 640 x 480 graphics input 4 : 2 : 2 Y-CB-CR graphics input (format 0) 4 : 4 : 4 RGB graphics input (format 3) input demultiplex phase: LSB = LOW input demultiplex phase: LSB = HIGH input demultiplex phase: MSB = LOW input demultiplex phase: MSB = HIGH slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar is active) master (FSVGC, VSVGC and HSVGC are outputs)
7.2 Input formatter
The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits EDGE1 and EDGE2 for correct operation. If Y-CB-CR is being applied as a 27 MB/s data stream, the output of the input formatter can be used directly to feed the video encoder block.
7.3 RGB LUT
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed color data is applied, the RAMs are addressed in parallel. The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 bytes x 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on.
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
9 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
7.4 Cursor insertion
A 32 dots x 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input through the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 8. Transparent means that the input pixels are passed through, the `cursor colors' can be programmed in separate registers. The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner.
Table 6: 7 pixel n + 3 D1 D0 Layout of a byte in the cursor bit map 6 5 pixel n + 2 D1 D0 4 3 pixel n + 1 D1 D0 D1 2 1 pixel n D0 0
For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the `hot spot', the other register controls the insertion position. The hot spot is the `tip' of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution.
Table 7: Byte 0 1 2 ... 6 7 ... 254 255 Cursor bit map 7 6 5 4 3 2 1 0 row 0 column 3 row 0 column 7 row 0 column 11 ... row 0 column 27 row 0 column 31 ... row 31 column 27 row 31 column 31 row 0 column 2 row 0 column 6 row 0 column 10 ... row 0 column 26 row 0 column 30 ... row 31 column 26 row 31 column 30 row 0 column 1 row 0 column 5 row 0 column 9 ... row 0 column 25 row 0 column 29 ... row 31 column 25 row 31 column 29 row 0 column 0 row 0 column 4 row 0 column 8 ... row 0 column 24 row 0 column 28 ... row 31 column 24 row 31 column 28
SAA7102_SAA7103_4
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Product data sheet
Rev. 04 -- 18 January 2006
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Cursor modes Cursor mode CMODE = 0 CMODE = 1 second cursor color first cursor color transparent auxiliary cursor color second cursor color first cursor color transparent inverted input
Table 8:
Cursor pattern 00 01 10 11
7.5 RGB Y-CB-CR matrix
RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR color space in this block. The color difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC.
7.6 Horizontal scaler
The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the color phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7102; SAA7103 input data is in accordance with "ITU-R BT.656", the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.
7.7 Vertical scaler and anti-flicker filter
The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 91. The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Due to the re-interlacing, the circuit can perform upscaling. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 7.17.
7.8 FIFO
The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. It is suggested to refer to Table 9 to Table 26 for some representative combinations.
7.9 Border generator
When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true color tint.
7.10 Oscillator and Discrete Time Oscillator (DTO)
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 18 MHz and 44 MHz.
7.11 Low-pass Clock Generation Circuit (CGC)
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies.
7.12 Encoder
7.12.1 Video path
The encoder generates luminance and color subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization
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Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
schemes. Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7102 only. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figure 8 and Figure 9. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband color signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher color bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figure 6 and Figure 7. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, color is provided on the subcarrier in 10-bit resolution. The numeric ratio between the Y and C outputs is in accordance with the standards.
7.12.2 Teletext insertion and encoding (not simultaneously with real-time control)
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Figure 15. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.
7.12.3 Video Programming System (VPS) encoding
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16.
7.12.4 Closed caption encoder
Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency.
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency.
7.12.5 Anti-taping (SAA7102 only)
For more information contact your nearest Philips Semiconductors sales office.
7.13 RGB processor
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and color difference signals and 2 times oversampling for luminance and 4 times oversampling for color difference signals is performed. The transfer curves of luminance and color difference components of RGB are illustrated in Figure 10 and Figure 11.
7.14 Triple DAC
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of the conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 ) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. If the SAA7102; SAA7103 is required to drive a second (auxiliary) VGA monitor, the DACs receive the signal directly from the cursor insertion block. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder.
7.15 Timing generator
The synchronization of the SAA7102; SAA7103 is able to operate in two modes; Slave mode and Master mode. In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is
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SAA7102; SAA7103
Digital video encoder
interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. Only vertical frequencies of 50 Hz and 60 Hz are allowed with the SAA7102; SAA7103. In Slave mode, it is not possible to lock the encoders color carrier to the line frequency with the PHRES bits. In the (more common) Master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figure 13 and Figure 14):
* * * * *
The horizontal offset The length of the active part of the line The distance from active start to first expected data The vertical offset separately for odd and even fields The number of lines per input field
In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7102; SAA7103 will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 101. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0.
7.16 I2C-bus interface
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and read, except two read only status bytes. The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data
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SAA7102; SAA7103
Digital video encoder
bytes following subaddress FFh. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. The I2C-bus slave address is defined as 88h.
7.17 Programming the SAA7102; SAA7103
In order to program the SAA7102; SAA7103 it is first necessary to determine the input and output field timings. The timings are controlled by decoding binary counters that index the position in the current line and field respectively. In both cases, 0 means the start of the sync pulse. At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. Some variables are defined below:
* * * * * * *
InPix: the number of active pixels per input line InPpl: the length of the entire input line in pixel clocks InLin: the number of active lines per input field/frame TPclk: the pixel clock period OutPix: the number of active pixels per output line OutLin: the number of active lines per output field TXclk: the encoder clock period (37.037 ns)
The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 62. ADWHS = 256 + 710 - OutPix (60 Hz); ADWHS = 284 + 702 - OutPix (50 Hz); ADWHE = ADWHS + OutPix x 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 70 to Table 72. 240 - OutLin 287 - OutLin FAL = 19 + --------------------------------- (60 Hz); FAL = 23 + --------------------------------- (50 Hz); 2 2 LAL = FAL + OutLin (all frequencies). Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line. The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. Thus:
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SAA7102; SAA7103
Digital video encoder
262.5 x 1716 x TXclk TPclk = ----------------------------------------------------------------------------------------- (60 Hz) InLin + 2 InPpl x integer ----------------------- x 262.5 OutLin 312.5 x 1728 x TXclk TPclk = ----------------------------------------------------------------------------------------- (50 Hz) and for the pixel clock generator InLin + 2 InPpl x integer ----------------------- x 312.5 OutLin TXclk 21 PCL = -------------- x 2 (all frequencies); see Table 74. TPclk The input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: FAL x 1716 x TXclk FAL x 1728 x TXclk YOFS = -------------------------------------------------- - 2 (60 Hz) YOFS = -------------------------------------------------- - 2 (50 Hz) InPpl x TPclk InPpl x TPclk In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. Once the timings are known the scaler can be programmed. XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX HLEN is fulfilled. Values given by the VESA display timings are preferred. HLEN = InPpl - 1 InPix XPIX = ------------2 OutPix XINC = ------------------ x 4096 InPix XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. YPIX = InLin YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. OutLin YSKIP YINC = ----------------------- x 1 + ---------------- x 4096 InLin + 2 4095 YINC YIWGTO = ------------- + 2048 2 YINC - YSKIP YIWGTE = ------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive.
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SAA7102; SAA7103
Digital video encoder
Due to the limited amount of memory it is not possible to get valid vertical scaler settings only from the formulae above. In some cases it is necessary to adjust the vertical offsets or the scaler increment to get valid settings. Table 9 to Table 26 show verified settings. They are organized in the following way: The tables are separate for the standard to be encoded, the input resolution and three different anti-flicker filter settings. Each table contains 5 vertical sizes with 5 different offsets. They are intended to be selected according to the current TV set. The corresponding horizontal resolutions of 640 pixels give proper aspect ratios. They can be adjusted according to the formulae above. The next line gives a minimum size intended to fit on the screen under all circumstances. The corresponding horizontal resolution is 620 pixels. Overscan is only possible with an input resolution of 800 x 600 pixels. Where possible, the corresponding settings are given on the last lines of the tables.
7.18 Input levels and formats
The SAA7102; SAA7103 accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with "ITU-R BT.601"; see Table 27. For C and CVBS outputs, deviating amplitudes of the color difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and color difference signals (GCD). Reference levels are measured with a color bar, 100 % white, 100 % amplitude and 100 % saturation.
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SAA7102; SAA7103
Digital video encoder
Table 9: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 400, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 0 1925590 YINC 2163 2163 2163 2163 2163 2181 2181 2181 2181 2181 2202 2202 2202 2202 2202 2222 2222 2222 2222 2222 2245 2245 2245 2245 2245 0 2079 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 52 56 60 63 67 50 54 57 61 65 47 51 55 58 62 45 49 53 56 60 43 46 50 54 57 0 70 YOFSE 52 56 60 63 67 50 54 57 61 65 47 51 55 58 62 45 49 53 56 60 43 46 50 54 57 0 70 YIWGTO YIWGTE 3128 3128 3128 3128 3128 3138 3138 3138 3138 3138 3148 3148 3148 3148 3148 3158 3158 3158 3158 3158 3168 3168 3168 3168 3168 0 3087 1080 1080 1080 1080 1080 1090 1090 1090 1090 1090 1100 1100 1100 1100 1100 1110 1110 1110 1110 1110 1120 1120 1120 1120 1120 0 1039
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Overscan (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
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SAA7102; SAA7103
Digital video encoder
Table 10: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 400, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 0 1925590 YINC 3123 3123 3123 3123 3123 3135 3135 3135 3135 3135 3145 3145 3145 3145 3145 3155 3155 3155 3155 3155 3165 3165 3165 3165 3165 0 3087 YSKIP 1820 1820 1820 1820 1820 1790 1790 1790 1790 1790 1750 1750 1750 1750 1750 1720 1720 1720 1720 1720 1680 1680 1680 1680 1680 0 1980 YOFSO 52 56 60 64 67 50 54 58 61 65 48 51 55 59 63 45 49 53 56 60 43 47 50 54 58 0 70 YOFSE 52 56 60 64 67 50 54 58 61 65 48 51 55 59 63 45 49 53 56 60 43 47 50 54 58 0 70 YIWGTO YIWGTE 3668 3668 3668 3668 3668 3683 3683 3683 3683 3683 3698 3698 3698 3698 3698 3714 3714 3714 3714 3714 3729 3729 3729 3729 3729 0 3589 596 596 596 596 596 611 611 611 611 611 626 626 626 626 626 642 642 642 642 642 657 657 657 657 657 0 551
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 11: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 400, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 0 1925590 YINC 4094 4094 4094 4094 4094 4090 4090 4090 4088 4088 4093 4093 4093 4093 4093 4092 4092 4092 4092 4092 4090 4090 4090 4090 4090 0 4087 YSKIP 3655 3655 3655 3655 3655 3580 3580 3580 3580 3580 3510 3510 3510 3510 3510 3445 3445 3445 3445 3445 3370 3370 3370 3370 3370 0 3950 YOFSO 52 56 60 64 68 50 54 58 61 65 48 52 55 59 63 46 49 53 57 60 43 47 50 54 58 0 70 YOFSE 52 56 60 64 68 50 54 58 61 65 48 52 55 59 63 46 49 53 57 60 43 47 50 54 58 0 70 YIWGTO YIWGTE 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 0 4089 216 216 216 216 216 253 253 253 253 253 288 288 288 288 288 322 322 322 322 322 358 358 358 358 358 0 66
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 12: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 480, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 0 2309218 YINC 1804 1804 1804 1804 1804 1819 1819 1819 1819 1819 1836 1836 1836 1836 1836 1853 1853 1853 1853 1853 1870 1870 1870 1870 1870 0 1734 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 63 67 72 77 81 60 65 69 73 78 57 61 66 70 75 54 59 63 68 72 52 56 61 65 69 0 84 YOFSE 63 67 72 77 81 60 65 69 73 78 57 61 66 70 75 54 59 63 68 72 52 56 61 65 69 0 84 YIWGTO YIWGTE 2948 2948 2948 2948 2948 2957 2957 2957 2957 2957 2965 2965 2965 2965 2965 2974 2974 2974 2974 2974 2982 2982 2982 2982 2982 0 2941 900 900 900 900 900 909 909 909 909 909 917 917 917 917 917 926 926 926 926 926 934 934 934 934 934 0 866
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 13: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 480, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 0 2309218 YINC 2704 2704 2704 2704 2704 2730 2730 2730 2730 2730 2756 2756 2756 2756 2756 2781 2781 2781 2781 2781 2807 2807 2807 2807 2807 0 2602 YSKIP 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 0 2048 YOFSO 63 67 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 63 68 72 52 57 61 65 70 0 84 YOFSE 63 67 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 63 68 72 52 57 61 65 70 0 84 YIWGTO YIWGTE 3399 3399 3399 3399 3399 3412 3412 3412 3412 3412 3424 3424 3424 3424 3424 3437 3437 3437 3437 3437 3450 3450 3450 3450 3450 0 3348 327 327 327 327 327 340 340 340 340 340 352 352 352 352 352 365 365 365 365 365 378 378 378 378 378 0 276
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
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Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 14: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 640 x 480, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 0 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 0 241 PCL 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 0 2309218 YINC 3607 3607 3607 3607 3607 3639 3639 3639 3639 3639 3675 3675 3675 3675 3675 3709 3709 3709 3709 3709 3741 3741 3741 3741 3741 0 3471 YSKIP 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 0 4095 YOFSO 63 68 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 64 68 73 52 57 61 65 70 0 85 YOFSE 64 69 73 78 82 61 66 70 75 79 58 63 67 72 76 56 60 65 69 74 53 58 62 66 71 0 86 YIWGTO YIWGTE 3849 3849 3849 3849 3849 3866 3866 3866 3866 3866 3883 3883 3883 3883 3883 3900 3900 3900 3900 3900 3917 3917 3917 3917 3917 0 3781 3362 3362 3362 3362 3362 3413 3413 3413 3413 3413 3464 3464 3464 3464 3464 3515 3515 3515 3515 3515 3566 3566 3566 3566 3566 0 3158
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 15: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 800 x 600, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 18 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 259 241 PCL 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 3122659 3689981 YINC 1443 1443 1443 1443 1443 1457 1457 1457 1457 1457 1470 1470 1470 1470 1470 1484 1484 1484 1484 1484 1497 1497 1497 1497 1497 1642 1389 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 79 84 90 96 102 75 81 86 92 98 72 77 82 88 94 68 73 79 85 90 65 71 76 81 87 42 106 YOFSE 79 84 90 96 102 75 81 86 92 98 72 77 82 88 94 68 73 79 85 90 65 71 76 81 87 42 106 YIWGTO YIWGTE 2769 2769 2769 2769 2769 2776 2776 2776 2776 2776 2782 2782 2782 2782 2782 2789 2789 2789 2789 2789 2796 2796 2796 2796 2796 2867 2742 721 721 721 721 721 728 728 728 728 728 734 734 734 734 734 741 741 741 741 741 748 748 748 748 748 819 694
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 16: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 800 x 600, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 18 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 259 241 PCL 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 3122659 3689981 YINC 2165 2165 2165 2165 2165 2185 2185 2185 2185 2185 2205 2205 2205 2205 2205 2226 2226 2226 2226 2226 2246 2246 2246 2246 2246 2461 2083 YSKIP 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 YOFSO 79 85 91 96 102 75 81 87 92 98 72 77 83 89 94 68 74 80 85 90 65 71 76 81 87 42 106 YOFSE 79 85 91 96 102 75 81 87 92 98 72 77 83 89 94 68 74 80 85 90 65 71 76 81 87 42 106 YIWGTO YIWGTE 3129 3129 3129 3129 3129 3140 3140 3140 3140 3140 3150 3150 3150 3150 3150 3160 3160 3160 3160 3160 3170 3170 3170 3170 3170 3277 3089 57 57 57 57 57 68 68 68 68 68 78 78 78 78 78 88 88 88 88 88 98 98 98 98 98 205 17
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 17: TV line 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 241 204
Y scaler programming at NTSC, input frame size: 800 x 600, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 18 37 LAL 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 259 241 PCL 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 3122659 3689981 YINC 2887 2887 2887 2887 2887 2912 2912 2912 2912 2912 2941 2941 2941 2941 2941 2969 2969 2969 2969 2969 2994 2994 2994 2994 2994 3282 2778 YSKIP 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 YOFSO 79 85 91 96 102 76 81 87 92 98 72 78 83 89 94 69 74 80 85 90 65 71 76 82 87 42 106 YOFSE 80 86 92 97 103 77 82 88 93 99 73 79 84 90 95 70 75 81 86 91 66 72 77 83 88 43 107 YIWGTO YIWGTE 3490 3490 3490 3490 3490 3504 3504 3504 3504 3504 3517 3517 3517 3517 3517 3531 3531 3531 3531 3531 3544 3544 3544 3544 3544 3687 3436 2282 2282 2282 2282 2282 2323 2323 2323 2323 2323 2364 2364 2364 2364 2364 2405 2405 2405 2405 2405 2446 2446 2446 2446 2446 2875 2119
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 710 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
27 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 18: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 400, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 0 1559659 YINC 2600 2602 2602 2602 2602 2621 2623 2623 2623 2623 2641 2641 2641 2641 2641 2661 2661 2661 2661 2661 2684 2684 2684 2684 2684 0 2549 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 52 55 59 62 65 50 53 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 0 63 YOFSE 52 55 59 62 65 50 53 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 0 63 YIWGTO YIWGTE 3347 3347 3347 3347 3347 3357 3357 3357 3357 3357 3367 3367 3367 3367 3367 3377 3377 3377 3377 3377 3387 3387 3387 3387 3387 0 3321 1299 1299 1299 1299 1299 1309 1309 1309 1309 1309 1319 1319 1319 1319 1319 1329 1329 1329 1329 1329 1339 1339 1339 1339 1339 0 1273
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
28 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 19: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 400, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 0 1559659 YINC 3346 3346 3346 3346 3346 3360 3360 3360 3360 3360 3362 3362 3362 3362 3362 3378 3378 3378 3378 3378 3384 3384 3384 3384 3384 0 3322 YSKIP 1170 1170 1170 1170 1170 1150 1150 1150 1150 1150 1120 1120 1120 1120 1120 1100 1100 1100 1100 1100 1070 1070 1070 1070 1070 0 1240 YOFSO 53 56 59 62 65 51 54 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 0 63 YOFSE 53 56 59 62 65 51 54 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 0 63 YIWGTO YIWGTE 3996 3996 3996 3996 3996 4012 4012 4012 4012 4012 4070 4070 4070 4070 4070 4042 4042 4042 4042 4042 4057 4057 4057 4057 4057 0 3707 924 924 924 924 924 940 940 940 940 940 998 998 998 998 998 970 970 970 970 970 985 985 985 985 985 0 1039
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
29 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 20: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 400, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 42 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 301 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 0 1559659 YINC 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4093 4093 4093 4091 4091 4094 4094 4094 4093 4093 4092 4092 4092 4092 4092 0 4087 YSKIP 2350 2350 2350 2350 2350 2300 2300 2300 2300 2300 2250 2250 2250 2250 2250 2200 2200 2200 2200 2200 2150 2150 2150 2150 2150 0 2470 YOFSO 53 56 59 62 65 51 54 57 60 63 49 52 55 58 63 47 50 53 56 59 45 48 51 54 57 0 63 YOFSE 53 56 59 62 65 51 54 57 60 63 49 52 55 58 63 47 50 53 56 59 45 48 51 54 57 0 63 YIWGTO YIWGTE 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 0 4089 869 869 869 869 869 894 894 894 894 894 919 919 919 919 919 944 944 944 944 944 968 968 968 968 968 0 806
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
30 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 21: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 480, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 0 1870348 YINC 2168 2168 2168 2168 2168 2185 2185 2185 2185 2185 2202 2202 2202 2204 2202 2219 2219 2219 2219 2219 2238 2238 2238 2238 2238 0 2125 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 63 67 71 74 78 61 65 69 72 76 58 62 66 70 73 56 60 64 67 71 54 58 61 65 69 0 76 YOFSE 63 67 71 74 78 61 65 69 72 76 58 62 66 70 73 56 60 64 67 71 54 58 61 65 69 0 76 YIWGTO YIWGTE 3131 3131 3131 3131 3131 3139 3139 3139 3139 3139 3148 3148 3148 3148 3148 3156 3156 3156 3156 3156 3165 3165 3165 3165 3165 0 3110 1083 1083 1083 1083 1083 1091 1091 1091 1091 1091 1100 1100 1100 1100 1100 1108 1108 1108 1108 1108 1117 1117 1117 1117 1117 0 1062
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
31 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 22: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 480, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 0 1870348 YINC 3254 3254 3254 3254 3254 3277 3277 3277 3277 3277 3305 3305 3305 3305 3305 3328 3328 3328 3328 3328 3354 3354 3354 3354 3354 0 3108 YSKIP 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 0 1890 YOFSO 63 67 71 75 79 61 65 69 72 76 59 63 66 70 74 57 60 64 68 71 54 58 61 65 69 0 76 YOFSE 63 67 71 75 79 61 65 69 72 76 59 63 66 70 74 57 60 64 68 71 54 58 61 65 69 0 76 YIWGTO YIWGTE 3673 3673 3673 3673 3673 3686 3686 3686 3686 3686 3698 3698 3698 3698 3698 3711 3711 3711 3711 3711 3724 3724 3724 3724 3724 0 3600 601 601 601 601 601 614 614 614 614 614 626 626 626 626 626 639 639 639 639 639 652 652 652 652 652 0 607
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
32 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 23: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 640 x 480, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 0 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 0 291 PCL 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 0 1870348 YINC 4093 4093 4093 4093 4093 4090 4090 4090 4090 4090 4092 4092 4092 4092 4092 4088 4088 4088 4088 4088 4095 4095 4095 4095 4095 0 4088 YSKIP 3630 3630 3630 3630 3630 3570 3570 3570 3570 3570 3510 3510 3510 3510 3510 3450 3450 3450 3450 3450 3400 3400 3400 3400 3400 0 3780 YOFSO 64 67 71 75 79 61 65 69 73 76 59 63 66 70 74 57 60 64 68 71 54 58 62 65 69 0 76 YOFSE 64 67 71 75 79 61 65 69 73 76 59 63 66 70 74 57 60 64 68 71 54 58 62 65 69 0 76 YIWGTO YIWGTE 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4095 4095 4095 4095 4095 0 4090 228 228 228 228 228 258 258 258 258 258 288 288 288 288 288 318 318 318 318 318 345 345 345 345 345 0 152
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
33 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 24: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 800 x 600, full anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 22 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 310 291 PCL 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 2596864 2990569 YINC 1736 1736 1736 1736 1736 1749 1749 1749 1749 1749 1763 1763 1763 1763 1763 1778 1778 1778 1778 1778 1790 1790 1790 1790 1790 1960 1701 YSKIP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YOFSO 79 84 89 93 98 77 81 86 91 95 73 78 83 87 92 71 75 80 85 89 68 72 77 82 86 43 95 YOFSE 79 84 89 93 98 77 81 86 91 95 73 78 83 87 92 71 75 80 85 89 68 72 77 82 86 43 95 YIWGTO YIWGTE 2915 2915 2915 2915 2915 2922 2922 2922 2922 2922 2929 2929 2929 2929 2929 2935 2935 2935 2935 2935 2942 2942 2942 2942 2942 3027 2898 867 867 867 867 867 874 874 874 874 874 881 881 881 881 881 887 887 887 887 887 894 894 894 894 894 979 850
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
34 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 25: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 800 x 600, half anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 22 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 310 291 PCL 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 2596864 2990569 YINC 2604 2604 2604 2604 2604 2625 2625 2625 2625 2625 2645 2645 2645 2645 2645 2666 2666 2666 2666 2666 2686 2686 2686 2686 2686 2940 2553 YSKIP 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 YOFSO 80 84 89 94 98 77 82 86 91 96 74 79 83 88 92 71 75 80 85 89 68 73 77 82 86 43 96 YOFSE 80 84 89 94 98 77 82 86 91 96 74 79 83 88 92 71 75 80 85 89 68 73 77 82 86 43 96 YIWGTO YIWGTE 3349 3349 3349 3349 3349 3359 3359 3359 3359 3359 3369 3369 3369 3369 3369 3379 3379 3379 3379 3379 3390 3390 3390 3390 3390 3517 3323 277 277 277 277 277 287 287 287 287 287 297 297 297 297 297 307 307 307 307 307 318 318 318 318 318 445 251
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
35 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 26: TV line 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 288 250
Y scaler programming at PAL, input frame size: 800 x 600, no anti-flicker filter Offset -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 0 0 FAL 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 22 41 LAL 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 310 291 PCL 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 2596864 2990569 YINC 3473 3473 3473 3473 3473 3500 3500 3500 3500 3500 3527 3527 3527 3527 3527 3555 3555 3555 3555 3555 3582 3582 3582 3582 3582 3923 3405 YSKIP 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 YOFSO 80 84 89 94 99 77 82 87 91 96 74 79 83 88 93 71 76 80 85 89 68 73 78 82 87 44 96 YOFSE 81 85 90 95 100 78 83 88 92 97 75 80 84 89 94 72 77 81 86 90 69 74 79 83 88 45 97 YIWGTO YIWGTE 3783 3783 3783 3783 3783 3796 3796 3796 3796 3796 3810 3810 3810 3810 3810 3823 3823 3823 3823 3823 3837 3837 3837 3837 3837 4007 3748 3161 3161 3161 3161 3161 3202 3202 3202 3202 3202 3242 3242 3242 3242 3242 3284 3284 3284 3284 3284 3324 3324 3324 3324 3324 3836 3059
Regular size (horizontal TV size: 640 pixels, offset 10 pixels)
Full size (horizontal size: 702 pixels) Small size (horizontal size: 620 pixels)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
36 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
"ITU-R BT.601" signal component levels Signals [1] Y CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128 R 235 235 16 16 235 235 16 16 G 235 235 235 235 16 16 16 16 B 235 16 235 16 235 16 235 16 235 210 170 145 106 81 41 16
Table 27: Color White Yellow Cyan Green Magenta Red Blue Black
[1]
Transformation: R = Y + 1.3707 x (CR - 128) G = Y - 0.3365 x (CB - 128) - 0.6982 x (CR - 128) B = Y + 1.7324 x (CB - 128).
Table 28: Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 29: Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
SAA7102_SAA7103_4
Pin assignment for input format 0 Falling clock edge G3/Y3 G2/Y2 G1/Y1 G0/Y0 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 B2/CB2 B1/CB1 B0/CB0 Pin assignment for input format 1 Falling clock edge G2 G1 G0 B4 B3 B2 B1 B0 Rising clock edge X R4 R3 R2 R1 R0 G4 G3
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/CB-Y-CR Rising clock edge R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 R2/CR2 R1/CR1 R0/CR0 G7/Y7 G6/Y6 G5/Y5 G4/Y4
5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB
Product data sheet
Rev. 04 -- 18 January 2006
37 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Pin assignment for input format 2 Falling clock edge G2 G1 G0 B4 B3 B2 B1 B0 Pin assignment for input format 3 Falling clock edge n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) Rising clock edge n Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) Falling clock edge n + 1 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) Rising clock edge n + 1 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1) Rising clock edge R4 R3 R2 R1 R0 G5 G4 G3
Table 30: Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 31: Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 32: Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB
8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR
Pin assignment for input format 4 Rising clock edge n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) Rising clock edge n + 1 Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) Rising clock edge n + 2 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) Rising clock edge n + 3 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock)
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
38 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Pin assignment for input format 5 [1] Falling clock edge X X X X INDEX7 INDEX6 INDEX5 INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 Rising clock edge X X X X X X X X X X X X
Table 33: Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
[1]
8-bit non-interlaced index color
X = don't care.
Table 34: Pin PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Pin assignment for input format 6 Falling clock edge G4/Y4 G3/Y3 G2/Y2 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 G0/Y0 B2/CB2 B1/CB1 B0/CB0 Rising clock edge R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 G7/Y7 G6/Y6 G5/Y5 R2/CR2 R1/CR1 R0/CR0 G1/Y1
8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/CB-Y-CR
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
39 of 84
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
8.1 Bit allocation map
Table 35: Slave receiver (slave address 88h) Subaddress (hexadecimal) 00 01 to 15 16 17 18 19 1A 1B 26 27 28 29 2A 2B 2C 2D 2E to 37 38 39 3A 54 55 56 57 58 59 5A 5B
[1] [1] [1] [1] [1]
Product data sheet Rev. 04 -- 18 January 2006 40 of 84
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
8. Register description
Philips Semiconductors
Register function Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse B DAC adjust coarse MSM threshold Monitor sense mode Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Gain luminance for RGB Gain color difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase Gain U
7 VER2
6 VER1
[1] [1] [1] [1] [1]
5 VER0
[1] [1] [1] [1] [1]
4 CCRDO
[1] [1]
3 CCRDE
[1]
2
1 FSEQ
[1]
0 O_E
[1]
[1]
DACF3 RDACC3 GDACC3 BDACC3 MSMT3
[1]
DACF2 RDACC2 GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN
[1]
DACF1 RDACC1 GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17
[1] [1]
DACF0 RDACC0 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16
[1]
RDACC4 GDACC4 BDACC4 MSMT4
[1]
MSMT7 MSM CID7 WSS7 WSSON
[1]
MSMT6
[1]
MSMT5
[1]
Chip ID (02h or 03h, read only) 1C
CID6 WSS6
[1] [1] [1]
CID5 WSS5 WSS13 BS5 BE5 CG05 CG13
[1]
CID4 WSS4 WSS12 BS4 BE4 CG04 CG12
[1]
CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF
[1]
SRES CG07 CG15 CGEN VBSEN
[1] [1] [1]
CG06 CG14
[1]
CVBSEN1
[1] [1] [1] [1] [1]
CVBSEN0
[1] [1] [1] [1] [1]
CEN
[1]
SAA7102; SAA7103
[1]
GY4 GCD4 SYMP
[1]
GY3 GCD3 DEMOFF
[1]
GY2 GCD2 CSYNC
[1]
GY1 GCD1 Y2C EDGE2 VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1 GAINU1
GY0 GCD0 UV2C EDGE1 VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0 GAINU0
CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7 GAINU7
VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6 GAINU6
VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5 GAINU5
VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4 GAINU4
VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3 GAINU3
VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2 GAINU2
Digital video encoder
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Table 35: Slave receiver (slave address 88h) ...continued Subaddress (hexadecimal) 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 7 GAINV7 GAINU8 GAINV8 CCRS1
[1]
Product data sheet Rev. 04 -- 18 January 2006 41 of 84
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Philips Semiconductors
Register function Gain V Gain U MSB, black level Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH TTX request horizontal start TTX request horizontal delay CSYNC advance TTX odd request vertical start TTX odd request vertical end TTX even request vertical start
6 GAINV6
[1] [1]
5 GAINV5 BLCKL5 BLNNL5 BLNVB5
[1] [1]
4 GAINV4 BLCKL4 BLNNL4 BLNVB4
[1]
3 GAINV3 BLCKL3 BLNNL3 BLNVB3
[1] [1]
2 GAINV2 BLCKL2 BLNNL2 BLNVB2
[1]
1 GAINV1 BLCKL1 BLNNL1 BLNVB1
[1]
0 GAINV0 BLCKL0 BLNNL0 BLNVB0
[1]
CCRS0
[1]
DOWND
[1]
DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16
[1]
YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14
[1]
SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12
[1]
PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11
[1]
FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10
[1]
BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15
[1]
BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13
[1]
FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17
[1]
HTRIG7 HTRIG10
[1]
HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 ADWHE6
HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 ADWHE5
HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 ADWHE4 ADWHE8 TTXHS4
[1]
HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 ADWHE3
[1]
HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 ADWHE2
HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 ADWHE1
HTRIG0 VTRIG0
SAA7102; SAA7103
FLC0 SCCLN0 ADWHS0 ADWHE0 ADWHS8 TTXHS0 TTXHD0
[1]
CCEN1 ADWHS7 ADWHE7
[1]
ADWHE10 ADWHE9 TTXHS6
[1]
ADWHS10 ADWHS9 TTXHS2 TTXHD2
[1]
Digital video encoder
TTXHS7
[1]
TTXHS5
[1]
TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3 TTXEVS3
TTXHS1 TTXHD1
[1]
CSYNCA4 TTXOVS7 TTXOVE7 TTXEVS7
CSYNCA3 TTXOVS6 TTXOVE6 TTXEVS6
CSYNCA2 TTXOVS5 TTXOVE5 TTXEVS5
CSYNCA1 TTXOVS4 TTXOVE4 TTXEVS4
TTXOVS2 TTXOVE2 TTXEVS2
TTXOVS1 TTXOVE1 TTXEVS1
TTXOVS0 TTXOVE0 TTXEVS0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 35: Slave receiver (slave address 88h) ...continued Subaddress (hexadecimal) 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 to 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 7 TTXEVE7 FAL7 LAL7 TTX60
[1]
Product data sheet Rev. 04 -- 18 January 2006 42 of 84
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Philips Semiconductors
Register function TTX even request vertical end First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line FIFO status (read only) Pixel clock 0 Pixel clock 1 Pixel clock 2 Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB Vertical line skip
6 TTXEVE6 FAL6 LAL6 LAL8
[1]
5 TTXEVE5 FAL5 LAL5
[1] [1]
4 TTXEVE4 FAL4 LAL4 FAL8
[1]
3 TTXEVE3 FAL3 LAL3 TTXEVE8
[1]
2 TTXEVE2 FAL2 LAL2 TTXOVE8
[1]
1 TTXEVE1 FAL1 LAL1 TTXEVS8
[1]
0 TTXEVE0 FAL0 LAL0 TTXOVS8
[1]
LINE12 LINE20
LINE11 LINE19
LINE10 LINE18
LINE9 LINE17
LINE8 LINE16
LINE7 LINE15
LINE6 LINE14 OVFL PCL01 PCL09 PCL17
[1]
LINE5 LINE13 UDFL PCL00 PCL08 PCL16
[1]
PCL07 PCL15 PCL23
[1]
PCL06 PCL14 PCL22
[1]
PCL05 PCL13 PCL21
[1]
PCL04 PCL12 PCL20
[1]
PCL03 PCL11 PCL19
[1]
PCL02 PCL10 PCL18
[1]
XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11 YIWGTO7 YIWGTE7
XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10 YIWGTO6 YIWGTE6
XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9 YIWGTO5 YIWGTE5
XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8 YIWGTO4 YIWGTE4 YIWGTE8 YSKIP4
XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3
[1]
XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2 HSL PVS HLEN2 HLEN10 XINC2 YINC2 XINC10 YIWGTO2 YIWGTE2 YIWGTO1 0 YSKIP2
XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9 YIWGTO1 YIWGTE1 YIWGTO9 YSKIP1
XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0
SAA7102; SAA7103
YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 YIWGTO0 YIWGTE0 YIWGTO8 YSKIP0
XINC3 YINC3 XINC11 YIWGTO3 YIWGTE3 YIWGTO1 1 YSKIP3
Digital video encoder
YIWGTE11 YIWGTE10 YIWGTE9 YSKIP7 YSKIP6 YSKIP5
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 35: Slave receiver (slave address 88h) ...continued Subaddress (hexadecimal) A1 A2 A3 A4 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 7 BLEN BCY7 BCU7 BCV7 CC1R7 CC1G7 CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4 LUTOFF
[1]
Product data sheet Rev. 04 -- 18 January 2006 43 of 84
SAA7102_SAA7103_4 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Philips Semiconductors
Register function Blank enable for NI-bypass, vertical line skip MSB Border color Y Border color U Border color V Cursor color 1 R Cursor color 1 G Cursor color 1 B Cursor color 2 R Cursor color 2 G Cursor color 2 B Auxiliary cursor color R Auxiliary cursor color G Auxiliary cursor color B Horizontal cursor position Horizontal hot spot, MSB XCP Vertical cursor position Vertical hot spot, MSB YCP Input path control Cursor bit map Color look-up table
[1]
6
[1]
5
[1]
4
3 YSKIP11 BCY3 BCU3 BCV3 CC1R3 CC1G3 CC1B3 CC2R3 CC2G3 CC2B3 AUXR3 AUXG3 AUXB3 XCP3 XHS0 YCP3 YHS0 IF1
2 YSKIP10 BCY2 BCU2 BCV2 CC1R2 CC1G2 CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2
[1]
1 YSKIP9 BCY1 BCU1 BCV1 CC1R1 CC1G1 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 YCP9 MATOFF
0 YSKIP8 BCY0 BCU0 BCV0 CC1R0 CC1G0 CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 YCP8 DFOFF
BCY6 BCU6 BCV6 CC1R6 CC1G6 CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3 CMODE
BCY5 BCU5 BCV5 CC1R5 CC1G5 CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2 LUTL
BCY4 BCU4 BCV4 CC1R4 CC1G4 CC1B4 CC2R4 CC2G4 CC2B4 AUXR4 AUXG4 AUXB4 XCP4 XHS1 YCP4 YHS1 IF2
IF0
SAA7102; SAA7103
RAM address (see Table 102) RAM address (see Table 103)
All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
Digital video encoder
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
8.2 I2C-bus format
S
1000 1000
A
SUBADDRESS
A
DATA 0
A
............
DATA n
A
P
001aad411
a. to control registers
S
1000 1000
A
FEh
A
RAM ADDRESS
A
DATA 0
A
............
DATA n
A
P
001aad413
b. to cursor bit map (subaddress FEh)
S
1000 1000
A
FFh
A
RAM ADDRESS
A
DATA 0R
A
DATA 0G
A
DATA 0B
A
............
P
001aad414
c. to color look-up table (subaddress FFh)
See Table 36 for explanations.
Fig 4. I2C-bus write access
S
1000 1000
A
SUBADDRESS
A
Sr
1000 1001
A
DATA 0
Am
............
DATA n
Am
P
001aad415
a. to control registers
S 1000 1000 A
FEh or FFh
A
RAM ADDRESS
A
Sr 1000 1001
A
DATA 0 Am ..........
DATA n Am
P
001aad416
b. to cursor bit map or color LUT
See Table 36 for explanations.
Fig 5. I2C-bus read access
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
44 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Explanations of Figure 4 and Figure 5 Description START condition repeated START condition slave address acknowledge generated by the slave acknowledge generated by the master subaddress byte data byte continued data bytes and acknowledges STOP condition start address for RAM access
Table 36: Code S Sr
1000 100X [1] A Am SUBADDRESS [2] DATA -------P RAM ADDRESS
[1] [2]
X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
8.3 Slave receiver
Table 37: Common DAC adjust fine register, subaddress 16h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements DAC fine output voltage adjustment, 1 % steps for all DACs 0111 0110 0101 0100 0011 0010 0001 1000 1001 1010 1011 1100 1101 1110 1111 7% 6% 5% 4% 3% 2% 1% 0% -1 % -2 % -3 % -4 % -5 % -6 % -7 % 7 to 4 -
3 to 0 DACF[3:0] R/W
0000* 0 %
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
45 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description Symbol Description must be programmed with logic 0 to ensure compatibility to future enhancements 7 to 5 -
Table 38: 17h to 19h 17h
Subaddress Bit
4 to 0 RDACC[4:0] output level coarse adjustment for RED DAC; default after reset is 1Bh for output of C signal 0 0000b 0.585 V to 1 1111b 1.240 V at 37.5 nominal for full-scale conversion 4 to 0 GDACC[4:0] output level coarse adjustment for GREEN DAC; default after reset is 1Bh for output of VBS signal 0 0000b 0.585 V to 1 1111b 1.240 V at 37.5 nominal for full-scale conversion 4 to 0 BDACC[4:0] output level coarse adjustment for BLUE DAC; default after reset is 1Fh for output of CVBS signal 0 0000b 0.585 V to 1 1111b 1.240 V at 37.5 nominal for full-scale conversion MSM threshold, subaddress 1Ah, bit description Description monitor sense mode threshold for DAC output voltage, should be set to 70h
18h
19h
Table 39: Bit
Symbol
7 to 0 MSMT[7:0]
Table 40: Monitor sense mode register, subaddress 1Bh, bit description Legend: * = default value after reset. Bit 7 Symbol Access Value Description MSM R/W 0* 1 6 to 3 2 R/W 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid on must be programmed with logic 0 to ensure compatibility to future enhancements check comparator at DAC on pin RED_CR_C 0 1 1 GCOMP R 0 1 0 BCOMP R 0 1 active, output is loaded inactive, output is not loaded check comparator at DAC on pin GREEN_VBS_CVBS active, output is loaded inactive, output is not loaded check comparator at DAC on pin BLUE_CB_CVBS active, output is loaded inactive, output is not loaded
RCOMP R
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
46 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 41: Wide screen signal registers, subaddresses 26h and 27h, bit description Legend: * = default value after reset. Subaddress Bit 27h 7 6 Symbol WSSON Access Value Description R/W R/W 0* 1 0 wide screen signalling output is disabled wide screen signalling output is enabled must be programmed with logic 0 to ensure compatibility to future enhancements wide screen signalling bits, reserved wide screen signalling bits, subtitles wide screen signalling bits, enhanced services wide screen signalling bits, aspect ratio
5 to 3 WSS[13:11] R/W 2 to 0 WSS[10:8] 26h 7 to 4 WSS[7:4] 3 to 0 WSS[3:0] R/W R/W R/W
Table 42: Real-time control and burst start register, subaddress 28h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description R/W R/W 21h* 19h* 0 must be programmed with logic 0 to ensure compatibility to future enhancements starting point of burst in clock cycles PAL: BS = 33; strapping pin FSVGC tied to HIGH NTSC: BS = 25; strapping pin FSVGC tied to LOW 7 and 6 5 to 0 BS[5:0]
Table 43: Sync reset enable and burst end register, subaddress 29h, bit description Legend: * = default value after reset. Bit 7 Symbol Access Value Description SRES R/W 0* 1 pin TTX_SRES accepts a teletext bit stream (TTX) pin TTX_SRES accepts a sync reset input (SRES); a HIGH impulse resets synchronization of the encoder (first field, first line) must be programmed with logic 0 to ensure compatibility to future enhancements ending point of burst in clock cycles 1Dh* 1Dh* PAL: BE = 29; strapping pin FSVGC tied to HIGH NTSC: BE = 29; strapping pin FSVGC tied to LOW
6 5 to 0
BE[5:0]
R/W R/W
0
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
47 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit description Legend: * = default value after reset. Subaddress Bit 2Ch 7 Symbol CGEN Access Value Description R/W 0* 1 6 to 4 R/W 0 copy generation data output disabled enabled must be programmed with logic 0 to ensure compatibility to future enhancements LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format.
Table 44:
3 to 0 CG[19:16] R/W 2Bh 2Ah 7 to 0 CG[15:8] 7 to 0 CG[7:0]
Table 45: Output port control register, subaddress 2Dh, bit description Legend: * = default value after reset. Bit 7 Symbol VBSEN Access Value Description R/W 0 1* 6 CVBSEN1 R/W 0* 1 5 CVBSEN0 R/W 0 1* 4 CEN R/W 0 1* 3 ENCOFF R/W 0* 1 2 CLK2EN R/W 0 1* 1 and 0 R/W 0 pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) luminance (VBS) signal pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal CVBS signal pin BLUE_CB_CVBS provides a component BLUE (B) or color difference BLUE (CB) signal CVBS signal pin RED_CR_C provides a component RED (R) or color difference RED (CR) signal chrominance signal (C) as modulated subcarrier for S-video encoder active bypass, DACs are provided with RGB signal after cursor insertion block pin TTXRQ_XCLKO2 provides teletext request signal (TTXRQ) buffered crystal clock divided by two (13.5 MHz) must be programmed with logic 0 to ensure compatibility to future enhancements
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
48 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 46: Gain luminance for RGB register, subaddress 38h, bit description Legend: * = default value after reset. Bit 7 to 5 4 to 0 Symbol Access Value Description R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements Gain luminance of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application.
GY[4:0] R/W
Table 47: Gain color difference for RGB register, subaddress 39h, bit description Legend: * = default value after reset. Bit 7 to 5 4 to 0 Symbol Access Value Description R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements Gain color difference of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application.
GCD[4:0] R/W
Table 48: Input port control 1 register, subaddress 3Ah, bit description Legend: * = default value after reset. Bit 7 Symbol CBENB Access Value Description R/W R/W R/W 0* 1 3 DEMOFF R/W 0* 1 2 CSYNC R/W 0 1 1 Y2C R/W 0 1* 0 UV2C R/W 0 1* 0 1 6 and 5 4 SYMP 0 data from input ports is encoded color bar with fixed colors is encoded must be programmed with logic 0 to ensure compatibility to future enhancements horizontal and vertical trigger taken from FSVGC or both VSVGC and HSVGC decoded out of `ITU-R BT.656' compatible data at PD port Y-CB-CR to RGB dematrix active bypassed pin HSM_CSYNC provides horizontal sync for non-interlaced VGA components output (at PIXCLK) composite sync for interlaced components output (at XTAL clock) input luminance data twos complement from PD input port straight binary from PD input port input color difference data twos complement from PD input port straight binary from PD input port
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
49 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 49: VPS enable, input control 2, subaddress 54h, bit description Legend: * = default value after reset. Bit 7 Symbol Access Value Description VPSEN R/W 0* 1 6 to 2 1 R/W 0 video programming system data insertion is disabled in line 16 is enabled must be programmed with logic 0 to ensure compatibility to future enhancements internal PPD2 data is sampled with 0 1* 0 EDGE1 R/W 0* 1 Table 50: rising clock edges falling clock edges; see Table 28 to Table 34 internal PPD1 data is sampled with rising clock edges falling clock edges; see Table 28 to Table 34
EDGE2 R/W
VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit description [1] Symbol Access Value Description R/W fifth byte of video programming system data eleventh byte of video programming system data twelfth byte of video programming system data thirteenth byte of video programming system data fourteenth byte of video programming system data 7 to 0 VPS5[7:0]
Subaddress Bit 55h 56h 57h 58h 59h
[1]
7 to 0 VPS11[7:0] R/W 7 to 0 VPS12[7:0] R/W 7 to 0 VPS13[7:0] R/W 7 to 0 VPS14[7:0] R/W
In line 16; LSB first; all other bytes are not relevant for VPS.
Table 51: Chrominance phase register, subaddress 5Ah, bit description Legend: * = default value after reset. Bit 7 to 0 Symbol Access Value Description 00h* phase of encoded color subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees PAL B/G and data from input ports in Master mode PAL B/G and data from look-up table NTSC M and data from input ports in Master mode NTSC M and data from look-up table CHPS[7:0] R/W
6Bh 16h 25h 46h
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
50 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 52: 5Bh 5Dh
Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description Symbol GAINU[8:0] [1] Conditions white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76h) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7Dh) 6 5 to 0 BLCKL[5:0] [2] Remarks GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal 7 to 0 7
Subaddress Bit
must be programmed with logic 0 to ensure compatibility to future enhancements white-to-sync = 140 IRE [3] BLCKL = 0 [3] IRE [4] BLCKL = 63 (3Fh) [3] white-to-sync = 143 BLCKL = 0 [4] (3Fh) [4] BLCKL = 63 recommended value: BLCKL = 58 (3Ah) output black level = 29 IRE output black level = 49 IRE recommended value: BLCKL = 51 (33h) output black level = 27 IRE output black level = 47 IRE
[1] [2] [3] [4]
Variable gain for CB signal; input representation in accordance with `ITU-R BT.601'. Variable black level; input representation in accordance with `ITU-R BT.601'. Output black level/IRE = BLCKL x 2/6.29 + 28.9. Output black level/IRE = BLCKL x 2/6.18 + 26.5.
Table 53: 5Ch 5Eh
Gain V and gain V MSB, blanking level registers, subaddresses 5Ch and 5Eh, bit description Symbol GAINV[8:0] [1] Conditions white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5h) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFh) 6 5 to 0 BLNNL[5:0] [2] Remarks GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal 7 to 0 7
Subaddress Bit
must be programmed with logic 0 to ensure compatibility to future enhancements white-to-sync = 140 IRE [3] BLNNL = 0 [3] IRE [4] BLNNL = 63 (3Fh) [3] white-to-sync = 143 BLNNL = 0 [4] (3Fh) [4] BLNNL = 63 recommended value: BLNNL = 46 (2Eh) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35h) output blanking level = 26 IRE output blanking level = 46 IRE
[1] [2] [3] [4]
Variable gain for CR signal; input representation in accordance with `ITU-R BT.601'. Variable blanking level. Output black level/IRE = BLNNL x 2/6.29 + 25.4. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35h.
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
CCR and blanking level VBI register, subaddress 5Fh, bit description Symbol Access Value Description R/W 00 01 10 11 select cross-color reduction filter in luminance; for overall transfer characteristic of luminance see Figure 8 no cross-color reduction cross-color reduction #1 active cross-color reduction #2 active cross-color reduction #3 active variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 54: Bit
7 and 6 CCRS[1:0]
5 to 0
BLNVB[5:0] R/W
-
Table 55: Standard control register, subaddress 61h, bit description Legend: * = default value after reset. Bit 7 Symbol DOWND Access Value Description R/W 0* 1 6 DOWNA R/W 0* 1 5 4 YGS R/W R/W 0 1 3 2 SCBW R/W R/W 0 0 digital core in normal operational mode in Sleep mode and is reactivated with an I2C-bus address DACs in normal operational mode in Power-down mode must be programmed with logic 0 to ensure compatibility to future enhancements luminance gain for white - black 100 IRE 92.5 IRE including 7.5 IRE set-up of black must be programmed with logic 0 to ensure compatibility to future enhancements bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figure 6 and Figure 7) 0 1* 1 PAL R/W 0 1 0 FISE R/W 0 1 enlarged standard encoding NTSC (non-alternating V component) PAL (alternating V component) total pixel clocks per line 864 858
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Product data sheet
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 56: Burst amplitude register, subaddress 62h, bit description Legend: * = default value after reset, ^ = recommended value. Bit 7 Symbol Access Value Description R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements amplitude of color burst; input representation in accordance with `ITU-R BT.601' 3Fh (63)^ 2Dh (45)^ 43h (67)^ white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding; BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding; BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding; BSTA = 0 to 1.90 x nominal
6 to 0 BSTA[6:0] R/W
2Fh white-to-black = 100 IRE; burst = 43 IRE; PAL encoding; (47)*^ BSTA = 0 to 3.02 x nominal Table 57: 66h 65h 64h 63h Subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description Symbol Access Value Description ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency); FSC[31:24] = most significant byte; FSC[07:00] = least significant byte [1] 7 to 0 FSC[31:24] R/W 7 to 0 FSC[23:16] R/W 7 to 0 FSC[15:08] R/W 7 to 0 FSC[07:00] R/W
Subaddress Bit
[1]
f fsc 32 FSC = round --------- x 2 f llc
Examples: a) NTSC M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F0 7C1Fh). b) PAL B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A09 8ACBh).
Table 58:
Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit description [1] Symbol Access Value Description first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field 7 to 0 L21O[07:00] R/W 7 to 0 L21O[17:10] R/W 7 to 0 L21E[07:00] R/W 7 to 0 L21E[17:10] R/W
Subaddress Bit 67h 68h 69h 6Ah
[1]
LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 59: Trigger control registers, subaddresses 6Ch and 6Dh, bit description Legend: * = default value after reset. Subaddress Bit 6Ch 6Dh Symbol Access Value Description R/W R/W 00h* 0h* 00h* sets the horizontal trigger phase related to chip-internal horizontal input [1] sets the vertical trigger phase related to chip-internal vertical input [2]
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
7 to 0 HTRIG[7:0] 4 to 0 VTRIG[4:0]
7 to 5 HTRIG[10:8] R/W
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] [2]
Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals. Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1Fh).
Table 60: Multi control register, subaddress 6Eh, bit description Legend: * = default value after reset. Bit 7 6 Symbol BLCKON Access Value Description R/W R/W 0 0* 1 5 and 4 PHRES[1:0] R/W 00 01 10 11 3 and 2 LDEL[1:0] R/W 00* 01 10 11 1 and 0 FLC[1:0] R/W 00* 01 10 11 must be programmed with logic 0 to ensure compatibility to future enhancements encoder in normal operation mode output signal is forced to blanking level selects the phase reset mode of the color subcarrier generator no subcarrier reset subcarrier reset every two lines subcarrier reset every eight fields subcarrier reset every four fields selects the delay on luminance path with reference to chrominance path no luminance delay 1 LLC luminance delay 2 LLC luminance delay 3 LLC luminance delay field length control interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 61: Closed caption, teletext enable register, subaddress 6Fh, bit description Legend: * = default value after reset. Bit Symbol Access Value Description R/W 00* 01 10 11 enables individual line 21 encoding line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields 7 and 6 CCEN[1:0]
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Closed caption, teletext enable register, subaddress 6Fh, bit description
...continued
Table 61: Bit 5
Symbol TTXEN
Access Value Description R/W 0* 1 teletext insertion disabled enabled selects the actual line, where closed caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
4 to 0
SCCLN[4:0] R/W
-
Table 62:
Active Display Window Horizontal (ADWH) start and end registers, subaddresses 70h to 72h, bit description Symbol Access Value Description R/W active display window horizontal start; defines the start of the active TV display portion after the border color [1] active display window horizontal end; defines the end of the active TV display portion before the border color [1] must be programmed with logic 0 to ensure compatibility to future enhancements active display window horizontal end; defines the end of the active TV display portion before the border color [1] must be programmed with logic 0 to ensure compatibility to future enhancements active display window horizontal start; defines the start of the active TV display portion after the border color [1] 7 to 0 ADWHS[7:0]
Subaddress Bit 70h
71h
7 to 0 ADWHE[7:0]
R/W
-
72h
7
-
R/W
0 -
6 to 4 ADWHE[10:8] R/W
3
-
R/W
0 -
2 to 0 ADWHS[10:8] R/W
[1]
Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.
Table 63: TTX request horizontal start register, subaddress 73h, bit description Legend: * = default value after reset. Bit 7 to 0 Symbol Access Value Description start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Figure 15 42h* 54h* if strapped to PAL if strapped to NTSC TTXHS[7:0] R/W
Table 64: TTX request horizontal delay register, subaddress 74h, bit description Legend: * = default value after reset and minimum value. Bit Symbol Access Value Description R/W R/W 0h 2h* must be programmed with logic 0 to ensure compatibility to future enhancements indicates the delay in clock cycles between rising edge of TTXRQ output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at pin TTX_SRES 7 to 4 3 to 0 TTXHD[3:0]
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
CSYNC advance register, subaddress 75h, bit description Access Value Description 000 advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks must be programmed with logic 0 to ensure compatibility to future enhancements
Table 65: Bit
Symbol
7 to 3 CSYNCA[4:0] R/W 2 to 0 R/W
Table 66: TTX odd request vertical start register, subaddress 76h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description with TTXOVS8 (see Table 72) first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field, line = (TTXOVS + 4) for M-systems and line = (TTXOVS + 1) for other systems 05h* 06h* if strapped to PAL if strapped to NTSC 7 to 0 TTXOVS[7:0] R/W
Table 67: TTX odd request vertical end register, subaddress 77h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description with TTXOVE8 (see Table 72) last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field, line = (TTXOVE + 3) for M-systems and line = TTXOVE for other systems 16h* 10h* if strapped to PAL if strapped to NTSC 7 to 0 TTXOVE[7:0] R/W
Table 68: TTX even request vertical start register, subaddress 78h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description with TTXEVS8 (see Table 72) first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field, line = (TTXEVS + 4) for M-systems and line = (TTXEVS + 1) for other systems 04h* 05h* if strapped to PAL if strapped to NTSC 7 to 0 TTXEVS[7:0] R/W
Table 69: TTX even request vertical end register, subaddress 79h, bit description Legend: * = default value after reset. Bit Symbol Access Value Description with TTXEVE8 (see Table 72) last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field, line = (TTXEVE + 3) for M-systems and line = TTXEVE for other systems 16h* 10h* if strapped to PAL if strapped to NTSC 7 to 0 TTXEVE[7:0] R/W
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
First active line register, subaddress 7Ah, bit description Access Value Description R/W with FAL8 (see Table 72) first active line = (FAL + 4) for M-systems and (FAL + 1) for other systems, measured in lines 00h coincides with the first field synchronization pulse
Table 70: Bit
Symbol
7 to 0 FAL[7:0]
Table 71: Bit
Last active line register, subaddress 7Bh, bit description Access Value Description R/W 00h with LAL8 (see Table 72) last active line = (LAL + 3) for M-systems and LAL for other system, measured in lines coincides with the first field synchronization pulse
Symbol
7 to 0 LAL[7:0]
Table 72: TTX mode, MSB vertical register, subaddress 7Ch, bit description Legend: * = default value after reset. Bit 7 6 5 4 3 2 1 0 Symbol TTX60 LAL8 FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8 Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W 0 0* 1 enables NABTS (FISE = 1) or European TTX (FISE = 0) enables world standard teletext 60 Hz (FISE = 1) see Table 71 must be programmed with logic 0 to ensure compatibility to future enhancements see Table 70 see Table 69 see Table 67 see Table 68 see Table 66
Table 73: 7Eh 7Fh
Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description [1] Symbol Access Value Description R/W individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) 7 to 0 LINE[12:5]
Subaddress Bit
7 to 0 LINE[20:13] R/W
[1]
This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Table 74: 81h 82h 83h
Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description Symbol Access Value Description defines the frequency of the synthesized pixel clock PIXCLKO; 7 to 0 PCL[07:00] R/W 7 to 0 PCL[15:08] 7 to 0 PCL[23:16]
Subaddress Bit
PCL f PIXCLK = ---------- x f XTAL x 8 ; 24 2
fXTAL = 27 MHz nominal 20 F63Bh 640 x 480 to NTSC M 1B 5A73h 640 x 480 to PAL B/G (as by strapping pins)
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Horizontal offset register, subaddress 90h, bit description Symbol XOFS[7:0] Description with XOFS[9:8] (see Table 79) horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output
Table 75: Bit 7 to 0
Table 76: Bit 7 to 0
Pixel number register, subaddress 91h, bit description Symbol XPIX[7:0] Description with XPIX[9:8] (see Table 79) pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses)
Table 77: Bit 7 to 0
Vertical offset odd register, subaddress 92h, bit description Symbol YOFSO[7:0] Description with YOFSO[9:8] (see Table 79) vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 78: Bit 7 to 0
Vertical offset even register, subaddress 93h, bit description Symbol YOFSE[7:0] Description with YOFSE[9:8] (see Table 79) vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 79: Bit 7 and 6 5 and 4 3 and 2 1 and 0 Table 80: Bit 7 to 0
MSBs register, subaddress 94h, bit description Symbol YOFSE[9:8] YOFSO[9:8] XPIX[9:8] XOFS[9:8] Description see Table 78 see Table 77 see Table 76 see Table 75
Line number register, subaddress 95h, bit description Symbol YPIX[7:0] Description with YPIX[9:8] (see Table 81) defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE - YOFSO
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description Symbol EFS Access Value Description R/W 0 1 in Slave mode frame sync signal at pin FSVGC ignored accepted polarity of CBO signal 0 1 normal (HIGH during active video) inverted (LOW during active video) from the SAA7102; SAA7103 the timing to the graphics controller is 0 1 master slave if hardware cursor insertion is active 0 1 set LOW for non-interlaced input signals set HIGH for interlaced input signals luminance sharpness booster 0 1 disabled enabled trigger event for the horizontal state machine (device is slave to HSVGC input) 0 1 not shifted shifted 128 PIXCLKs adapted to a late HSVGC see Table 80
Table 81: Bit 7
6
PCBN
R/W
5
SLAVE
R/W
4
ILC
R/W
3
YFIL
R/W
2
HSL
R/W
1 and 0 YPIX[9:8] Table 82: Bit 7
Sync control register, subaddress 97h, bit description Symbol HFS Access Value Description R/W 0 1 horizontal sync is derived from input signal (Save mode) at pin HSVGC a frame sync signal (Slave mode) at pin FSVGC (only if EFS is set HIGH) vertical sync (field sync) is derived from 0 1 input signal (Slave mode) at pin VSVGC a frame sync signal (Slave mode) at pin FSVGC (only if EFS is set HIGH) pin FSVGC is 0 1 input active output polarity of signal at pin FSVGC in output mode (Master mode) is 0 1 active HIGH; rising edge of the input signal is used in Slave mode active LOW; falling edge of the input signal is used in Slave mode
6
VFS
R/W
5
OFS
R/W
4
PFS
R/W
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Sync control register, subaddress 97h, bit description ...continued Symbol OVS Access Value Description R/W 0 1 pin VSVGC is input active output polarity of signal at pin VSVGC in output mode (Master mode) is 0 1 active HIGH; rising edge of the input signal is used in Slave mode active LOW; falling edge of the input signal is used in Slave mode pin HSVGC is 0 1 input active output polarity of signal at pin HSVGC in output mode (Master mode) is 0 1 active HIGH; rising edge of the input signal is used in Slave mode active LOW; falling edge of the input signal is used in Slave mode
Table 82: Bit 3
2
PVS
R/W
1
OHS
R/W
0
PHS
R/W
Table 83: Bit 7 to 0
Line length register, subaddress 98h, bit description Description with HLEN[10:8] (see Table 84) horizontal length;
Symbol HLEN[7:0]
number of PIXCLKs HLEN = ------------------------------------------------- - 1 line
Table 84: Bit 7 to 4 3 2 to 0 Input delay, MSB line length register, subaddress 99h, bit description Description input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel must be programmed with logic 0 to ensure compatibility to future enhancements
Symbol IDEL[3:0] -
HLEN[10:8] see Table 83 Horizontal increment register, subaddress 9Ah, bit description Description with XINC[11:8] (see Table 87) incremental fraction of the horizontal scaling
Table 85: Bit 7 to 0
Symbol XINC[7:0]
number of output pixels -------------------------------------------------------line engine; XINC = -------------------------------------------------------- x 4096 number of input pixels ----------------------------------------------------line
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Vertical increment register, subaddress 9Bh, bit description Symbol YINC[7:0] Description with YINC[11:8] (see Table 87) incremental fraction of the vertical scaling engine; YINC = --------------------------------------------------------------------- x 4096 -
Table 86: Bit 7 to 0
number of active output lines number of active input lines
Table 87: Bit 7 to 4 3 to 0 Table 88: Bit 7 to 0
MSBs vertical and horizontal increment register, subaddress 9Ch, bit description Symbol YINC[11:8] XINC[11:8] Description see Table 86 see Table 85
Weighting factor odd register, subaddress 9Dh, bit description Symbol YIWGTO[7:0] Description with YIWGTO[11:8] (see Table 90) weighting factor for the first line of the odd field; YIWGTO = ------------- + 2048 -
YINC 2
Table 89: Bit 7 to 0
Weighting factor even, subaddress 9Eh, bit description Symbol YIWGTE[7:0] Description with YIWGTE[11:8] (see Table 90) weighting factor for the first line of the even field; YIWGTE = -------------------------------------
YINC - YSKIP 2
Table 90: Bit 7 to 4 3 to 0 Table 91: Bit 7 to 0
Weighting factor MSB register, subaddress 9Fh, bit description Symbol Description YIWGTE[11:8] see Table 89 YIWGTO[11:8] see Table 88 Vertical line skip register, subaddress A0h, bit description Symbol YSKIP[7:0] Access Value Description R/W 000h with YSKIP[11:8] (see Table 92) vertical line skip; defines the effectiveness of the anti-flicker filter most effective FFFh anti-flicker filter switched off
Blank enable for NI-bypass, vertical line skip MSB register, subaddress A1h, bit description Legend: * = default value after reset. Bit 7 Symbol BLEN Access Value Description R/W 0* 1 6 to 4 3 to 0
SAA7102_SAA7103_4
Table 92:
for non-interlaced graphics in bypass mode no internal blanking forced internal blanking must be programmed with logic 0 to ensure compatibility to future enhancements see Table 91
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
YSKIP[11:8]
R/W R/W
000
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Border color Y register, subaddress A2h, bit description Symbol BCY[7:0] Description luminance portion of border color in underscan area
Table 93: Bit 7 to 0 Table 94: Bit 7 to 0 Table 95: Bit 7 to 0 Table 96: F0h F1h F2h Table 97: F3h F4h F5h Table 98:
Border color U register, subaddress A3h, bit description Symbol BCU[7:0] Description color difference portion of border color in underscan area
Border color V register, subaddress A4h, bit description Symbol BCV[7:0] Description color difference portion of border color in underscan area
Cursor color 1 R, G and B registers, subaddresses F0h to F2h, bit description Symbol Description 7 to 0 7 to 0 7 to 0 CC1R[7:0] RED portion of first cursor color CC1G[7:0] GREEN portion of first cursor color CC1B[7:0] BLUE portion of first cursor color
Subaddress Bit
Cursor color 2 R, G and B registers, subaddresses F3h to F5h, bit description Symbol Description 7 to 0 7 to 0 7 to 0 CC2R[7:0] RED portion of second cursor color CC2G[7:0] GREEN portion of second cursor color CC2B[7:0] BLUE portion of second cursor color
Subaddress Bit
Auxiliary cursor color R, G and B registers, subaddresses F6h to F8h, bit description Symbol Description 7 to 0 7 to 0 7 to 0 AUXR[7:0] RED portion of auxiliary cursor color AUXG[7:0] GREEN portion of auxiliary cursor color AUXB[7:0] BLUE portion of auxiliary cursor color
Subaddress Bit F6h F7h F8h Table 99:
Horizontal cursor position and horizontal hot spot, MSB XCP registers, subaddresses F9h and FAh, bit description Symbol XHS[4:0] XCP[7:0] Description horizontal hot spot of cursor 7 to 3 2 to 0 7 to 0
Subaddress Bit FAh F9h
XCP[10:8] horizontal cursor position
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 100: Vertical cursor position and vertical hot spot, MSB YCP registers, subaddresses FBh and FCh, bit description Subaddress Bit FCh 7 to 3 2 Symbol YHS[4:0] Description vertical hot spot of cursor must be programmed with logic 0 to ensure compatibility to future enhancements vertical cursor position
1 and 0 YCP[9:8] FBh 7 to 0 YCP[7:0]
Table 101: Input path control register, subaddress FDh, bit description Bit 7 Symbol Access Value Description color look-up table 0 1 6 CMODE R/W 0 1 5 LUTL R/W 0 1 4 to 2 IF[2:0] R/W 000 001 010 011 100 active bypassed cursor mode cursor mode; input color will be inverted auxiliary cursor color will be inserted LUT loading via input data stream inactive color and cursor LUTs are loaded input format 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91h and 94h set XPIX = number of active pixels/line) 8-bit non-interlaced index color 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) RGB to CR-Y-CB matrix 0 1 0 DFOFF R/W 0 1 active bypassed down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active bypassed LUTOFF R/W
101 110 1 MATOFF R/W
Table 102: Cursor bit map register, subaddress FEh, bit description Data byte CURSA Description RAM start address for cursor bit map; the byte following subaddress FEh points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 103: Color look-up table register, subaddress FFh, bit description Data byte COLSA Description RAM start address for color LUT; the byte following subaddress FFh points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
In subaddresses 5Bh, 5Ch, 5Dh, 5Eh and 62h all IRE values are rounded up.
8.4 Slave transmitter
Table 104: Status byte register, subaddress 00h, bit description Bit Symbol Access Value Description 101 version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 010 binary set immediately after the closed caption bytes of the odd field have been encoded reset after information has been written to the subaddresses 67h and 68h set immediately after the closed caption bytes of the even field have been encoded reset after information has been written to the subaddresses 69h and 6Ah during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) not first field of a sequence during even field during odd field 7 to 5 VER[2:0] R
4
CCRDO
R
1 0
3
CCRDE
R
1 0
2 1
FSEQ
R R
0 1 0
0
O_E
R
1 0
Table 105: Slave transmitter (slave address 89h) Register function Status byte Chip ID FIFO status Subaddress 00h 1Ch 80h Data byte D7 CID7 0 D6 CID6 0 D5 CID5 0 D4 CID4 0 D3 CID3 0 D2 CID2 0 D1 FSEQ CID1 OVFL D0 O_E CID0 UDFL VER2 VER1 VER0 CCRDO CCRDE 0
Table 106: Chip ID register, subaddress 1Ch, bit description Bit Symbol Access Value Description chip ID 02h 03h SAA7102 SAA7103 7 to 0 CID[7:0] R
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Digital video encoder
Table 107: FIFO status register, subaddress 80h, bit description Bit 1 Symbol Access Value Description R R 0h 0 1 0 UDFL R 0 1 no FIFO overflow FIFO overflow has occurred; this bit is reset after this subaddress has been read no FIFO underflow FIFO underflow has occurred; this bit is reset after this subaddress has been read OVFL 7 to 2 -
6 Gv (dB) 0 -6 -12 -18 -24
(1) (2)
mbe737
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) SCBW = 1. (2) SCBW = 0.
Fig 6. Chrominance transfer characteristic 1
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Digital video encoder
2 Gv (dB) 0
(1)
mbe735
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig 7. Chrominance transfer characteristic 2
6 Gv 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12
(4) (2) (3) (1)
mgd672
14 f (MHz)
(1) CCRS[1:0] = 01. (2) CCRS[1:0] = 10. (3) CCRS[1:0] = 11. (4) CCRS[1:0] = 00.
Fig 8. Luminance transfer characteristic 1 (excluding scaler)
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Digital video encoder
mbe736
1 Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS[1:0] = 00
Fig 9. Luminance transfer characteristic 2 (excluding scaler)
6 Gv 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12
mgb708
14 f (MHz)
Fig 10. Luminance transfer characteristic in RGB (excluding scaler)
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Digital video encoder
6 Gv 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12
mgb706
14 f (MHz)
Fig 11. Color difference transfer characteristic in RGB (excluding scaler)
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Digital video encoder
9. Limiting values
Table 108: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol Parameter VDDD VDDA Vi(A) Vi(n) Vi(D) VSS Tstg Tamb Vesd digital supply voltage analog supply voltage input voltage at analog inputs input voltage at pins XTALI, SDA and SCL input voltage at digital inputs or I/O pins voltage difference between VSSA(n) and VSSD(n) storage temperature ambient temperature electrostatic discharge voltage human body model machine model
[1] [2] [3]
[2] [3]
Conditions
Min -0.5 -0.5 -0.5 -0.5
Max +4.6 +4.6 +4.6
Unit V V V
VDDD + 0.5 V +4.6 +5.5 100 +150 70 2000 150 V V mV C C V V
outputs in 3-state outputs in 3-state
[1]
-0.5 -0.5 -65 0 -
Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. Class 2 according to JESD22-A114-B. Class A according to EIA/JESD22-A115-A.
10. Thermal characteristics
Table 109: Thermal characteristics Symbol Parameter Rth(j-a) thermal resistance from junction to ambient SAA7102E SAA7103E SAA7102H SAA7103H
[1]
Conditions in free air in free air in free air in free air
[1] [1] [1] [1]
Typ 38 38 53 53
Unit K/W K/W K/W K/W
The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area directly under the SAA7102; SAA7103 with a number of through-hole plating, connected to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended.
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Digital video encoder
11. Characteristics
Table 110: Characteristics VDDD = 3.0 V to 3.6 V; Tamb = 0 C to 70 C (typical values excluded); unless otherwise specified. Symbol Supplies VDDA VDDD IDDA IDDD Inputs VIL VIH ILI Ci LOW-level input voltage at all digital input pins except pins SDA and SCL HIGH-level input voltage at all digital input pins except pins SDA and SCL input leakage current input capacitance clocks data I/Os at high-impedance Outputs; all digital output pins except pin SDA VOL VOH VIL VIH Ii VOL Io TPIXCLK td(CLKD) tr tf Input timing tSU;DAT tHD;DAT fnom f/fnom input data set-up time input data hold time nominal frequency permissible deviation of nominal frequency
[5]
Parameter analog supply voltage digital supply voltage analog supply current digital supply current
Conditions
Min 3.15 3.0
[1] [2]
Typ Max 3.3 3.3 110 70 3.45 3.6 140 90 +0.8
Unit V V mA mA V
1 1 -0.5 2.0 -
VDDD + 0.3 V 10 10 8 8 A pF pF pF
LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDA) output current cycle time delay from PIXCLKO to PIXCLKI duty factor rise time fall time
IOL = 2 mA IOH = -2 mA
2.4 -0.5 0.7VDDD
50 50 27 10-6 -
0.4 0.3VDDD +10 0.4 100 60 60 3 3 +50 x 10-6
V V V A V mA ns ns % % ns ns ns ns MHz
I2C-bus; pins SDA and SCL VDDD + 0.3 V
Vi = LOW or HIGH IOL = 3 mA during acknowledge
[3] [4]
-10 3 22.5 40 40
[3] [3]
Clock timing; pins PIXCLKI and PIXCLKO
tHIGH/TPIXCLK tHIGH/TCLKO2; output
[3]
5 0 -50 x
Crystal oscillator
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Digital video encoder
Table 110: Characteristics ...continued VDDD = 3.0 V to 3.6 V; Tamb = 0 C to 70 C (typical values excluded); unless otherwise specified. Symbol Tamb CL RS C1 C0 Co(L) to(h) to(d) Parameter ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) output load capacitance output hold time output delay time see Table 111 see Table 111 see Table 111 see Table 111 Conditions Min 0 8 1.2 2.8 8 2 -3 dB 15 Typ Max 1.5 3.5 70 80 1.8 4.2 40 16 Unit C pF fF pF pF ns ns V V V V % MHz LSB LSB Crystal specification
Data and reference signal output timing
CVBS and RGB outputs Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) Vo(VBS)(p-p) Vo(C)(p-p) Vo(RGB)(p-p) Vo RL BDAC ILElf(DAC) DLElf(DAC) output voltage VBS (S-video) (peak-to-peak value) output voltage C (S-video) (peak-to-peak value) output voltage R, G, B (peak-to-peak value) inequality of output signal voltages load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs 1.23 1.0 -
0.89 0.7 2 3 1
37.5 -
[1] [2] [3] [4] [5]
Minimum value for I2C-bus bit DOWNA = 1. Minimum value for I2C-bus bit DOWND = 1. The data is for both input and output direction. This parameter is arbitrary, if PIXCLKI is looped through the VGC. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency.
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Digital video encoder
TPIXCLK tHIGH 2.4 V PIXCLKO 1.5 V 0.4 V td(CLKD) tf tr 2.0 V PIXCLKI 1.5 V 0.8 V tHD;DAT tSU;DAT PDn 0.8 V to(d) to(h) any output 0.4 V
mhb904
tHD;DAT tSU;DAT 2.0 V
2.4 V
Fig 12. Input/output timing specification
HSVGC
CBO
PD XOFS IDEL XPIX HLEN
mhb905
Fig 13. Horizontal input timing
HSVGC
VSVGC
CBO YOFS YPIX
mhb906
Fig 14. Vertical input timing
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Digital video encoder
11.1 Teletext timing
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbit/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbit/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbit/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings.
CVBS/Y t TTX text bit #: TTX_SRES t PD TTXRQ_XCLKO2
mhb891
t i(TTXW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
t FD
Fig 15. Teletext timing
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12. Application information
Philips Semiconductors
BST [0:2] VDDA3_2 VDDA3_1 BST0 BST1 BST2 VDD3_2 VDD3_1 10 40 VDDD1 VDDD2 36 29 VDDA2 VDDA1 TDI TDO SCL SDA 37 TRST 11 12 SCL SDA R10 75 AGND R11 75 AGND R12 75 AGND FLTR [0:2] RED_CR_C GREEN_VBS_CVBS BLUE_CB_CVBS VSM 27 28 30 25 26 Y1 XTALO XTALI 34 35 VDD3_0 R2 TTX_SRES TTXRQ_XCLKO2 23 24 27 MHz C8 10 pF L1 10 H C7 10 pF C9 1 nF FLTR0 FLTR1 FLTR2
6 TMS
38 7 TDI TDO
8 TCK
PD [0:11]
TP5 HSVGC
TP4 CBO
PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
4 3 2 1 44 43 42 41 16 17 18 19
PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
VSM HSM_CSYNC
SAA7102H SAA7103H
HSM_CSYNC
HSVGC VSVGC FSVGC CBO
22 14
HSVGC VSVGC
13 FSVGC 21 CBO
SAA7102; SAA7103
TTX_SRES TTXRQ_XCLKO2 PIXCLKO PIXCLKI RESET VSSD2 VSSD1 VSSA1 DUMP RSET
4.7 k S1 CP1 22 F JP9 RESET DGND RESET
DGND
TP3 XCLKO2 VDDA3_1 VDDA3_2 C1 100 nF C4 100 nF R3 0 AGND DGND VDD3_1 VDD3_2 C2 100 nF C3 100 nF
33
39
9
32 31
15
20
5
Digital video encoder
AGND
DGND R9 12 R8 1 k AGND JP10 CLK SHORT R7 22 R6 22
RESET PIXCLKO
PIXCLKI
mhb913
74 of 84
Fig 16. Application circuit
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
C16 120 pF L2 2.7 H C10 390 pF C13 560 pF L3 2.7 H
AGND
JP11
JP12
FIN FILTER 1 = byp. ll act.
FOUT
mhb912
Fig 17. FLTR0, FLTR1 and FLTR2 of Figure 16
12.1 Analog output voltages
The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Table 52 to Table 56 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 111 for a 100100 color bar signal. By setting the reference currents of the DACs as shown in Table 111, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16h, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0 %. If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output.
Table 111: Digital output signals conversion range Set/out Digital settings Digital output Analog settings Analog output CVBS, sync tip-to-white see Table 52 to Table 56 1014 e.g. B DAC = 1Fh 1.23 V (p-p) VBS, sync tip-to-white see Table 52 to Table 56 881 e.g. G DAC = 1Bh 1.00 V (p-p) RGB, black-to-white see Table 46 and Table 47 876 e.g. R DAC = G DAC = B DAC = 0Bh 0.70 V (p-p)
12.2 Suggestions for a board layout
Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 resistor directly at the supply stage. Use separate supply lines for the analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC).
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Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. Be careful of hidden layout capacitors around the crystal application. Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy.
13. Test information
13.1 Boundary scan test
The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7102; SAA7103 follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 112. Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) of the SAA7102; SAA7103 is available on request.
Table 112: BST instructions supported by the SAA7102; SAA7103 Instruction BYPASS EXTEST SAMPLE Description This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number.
CLAMP
IDCODE
13.1.1 Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.
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Digital video encoder
13.1.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Figure 18.
MSB 31 TDI 28 27 0111 0001 0000 0010 16-bit part number 12 11 000 0001 0101 11-bit manufacturer identification 1
LSB 0 1 TDO
0010
4-bit version code
mhb909
a. SAA7102.
MSB 31 TDI 28 27 0111 0001 0000 0011 16-bit part number 12 11 000 0001 0101 11-bit manufacturer identification 1 1 LSB 0 TDO
0010
4-bit version code
mhb910
b. SAA7103. Fig 18. 32 bits of identification code
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Digital video encoder
14. Package outline
LBGA156: plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm SOT700-1
D
B
A
ball A1 index area A E A2 A1 detail X
e1 e
1/2 e
C b
v M C A B w M C
y1 C
y
P N M L K J H G F E D C B A 1/2 e
e
e2
ball A1 index area
1 2
3 4
5 6
7 8
9 10
11 12
13 14
X
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.65 A1 0.45 0.35 A2 1.20 0.95 b 0.55 0.45 D 15.2 14.8 E 15.2 14.8 e 1 e1 13 e2 13 v 0.25 w 0.1 y 0.12 y1 0.35
OUTLINE VERSION SOT700-1
REFERENCES IEC --JEDEC MO-192 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 01-05-11 01-11-06
Fig 19. Package outline SOT700-1 (LBGA156)
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Digital video encoder
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-01 03-02-25
Fig 20. Package outline SOT307-2 (QFP44)
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15. Soldering
15.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
15.5 Package related soldering information
Table 113: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
81 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
16. Revision history
Table 114: Revision history Document ID Modifications: Release date Data sheet status Product data sheet Change notice Doc. number Supersedes SAA7102_SAA7103_3 SAA7102_SAA7103_4 20060118 CPCN200505019 -
* * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors Table 4: pin SCL corrected from I to I(/O) and updated description Table 4: updated description for pin SDA Package outline changed from SOT472-1 to SOT700-1 Product specification Product specification Product specification 9397 750 11445 SAA7102_03_2 9397 750 09214 SAA7102_03_1 9397 750 08371 -
SAA7102_SAA7103_3 20040301 SAA7102_03_2 SAA7102_03_1 20020218 20010925
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
82 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
17. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with Macrovision copyright protection technology -- This product incorporates copyright protection technology that is protected by method claims of certain U.S. patents and other intellectual property rights owned by Macrovision Corporation and other rights owners. Use of this copyright protection technology must be authorized by Macrovision Corporation and is intended for home and other limited viewing uses only, unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited.
19. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
20. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V.
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
SAA7102_SAA7103_4
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 -- 18 January 2006
83 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.12.1 7.12.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . 9 Input formatter . . . . . . . . . . . . . . . . . . . . . . . . . 9 RGB LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cursor insertion . . . . . . . . . . . . . . . . . . . . . . . 10 RGB Y-CB-CR matrix. . . . . . . . . . . . . . . . . . . . 11 Horizontal scaler . . . . . . . . . . . . . . . . . . . . . . . 11 Vertical scaler and anti-flicker filter . . . . . . . . . 11 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Border generator. . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator and Discrete Time Oscillator (DTO) 12 Low-pass Clock Generation Circuit (CGC) . . . 12 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Teletext insertion and encoding (not simultaneously with real-time control). . . . . . . 13 7.12.3 Video Programming System (VPS) encoding. 13 7.12.4 Closed caption encoder . . . . . . . . . . . . . . . . . 13 7.12.5 Anti-taping (SAA7102 only) . . . . . . . . . . . . . . 14 7.13 RGB processor . . . . . . . . . . . . . . . . . . . . . . . . 14 7.14 Triple DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.15 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 14 7.16 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 15 7.17 Programming the SAA7102; SAA7103. . . . . . 16 7.18 Input levels and formats . . . . . . . . . . . . . . . . . 18 8 Register description . . . . . . . . . . . . . . . . . . . . 40 8.1 Bit allocation map . . . . . . . . . . . . . . . . . . . . . . 40 8.2 I2C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.4 Slave transmitter . . . . . . . . . . . . . . . . . . . . . . . 64 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 69 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1 Teletext timing . . . . . . . . . . . . . . . . . . . . . . . . . 73 12 Application information. . . . . . . . . . . . . . . . . . 74 12.1 Analog output voltages . . . . . . . . . . . . . . . . . . 75 12.2 Suggestions for a board layout . . . . . . . . . . . . 75 13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 13.1 Boundary scan test . . . . . . . . . . . . . . . . . . . . 13.1.1 Initialization of boundary scan circuit . . . . . . . 13.1.2 Device identification codes. . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 15.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15.5 Package related soldering information . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information . . . . . . . . . . . . . . . . . . . . 76 76 76 77 78 80 80 80 80 81 81 82 83 83 83 83 83
(c) Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 January 2006 Document number: SAA7102_SAA7103_4
Published in The Netherlands

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